The present invention generally relates to high performance push-pull drivers for use in logic and memory array chips and, more particularly, to such a driver in which the output negative-going transition is made substantially as fast as the positive-going transition.
High performance push-pull drivers are desired in logic and memory array chips because of their superior driving capabilities with capacitance-loaded lines. However, such state-of-the-art drivers in use today suffer a common problem. That is, the output negative-going transition is slower than the up-going one. Such a performance problem often is due to the fact that the open collector pull-down transistor in a conventional design is biased to shut off (or nearly so) when the output is high. More time is required to turn on or to bias up the conduction of the pull-down transistor when compared to the time required to turn on the emitter follower conventionally used as the pull-up transistor. The result is non-symmetrical turn ON and turn OFF circuit delays whereby overall circuit speed is impacted.
For example, in U.S. Pat. No. 4,559,458, for Temperature Tracking and Supply Voltage Independent Line Driver for ECL Circuits, issued in the name of Bing-Fong Ma on Dec. 17, 1985, a pull down transistor pair is quiescently biased to low standby current. A transition detection circuit increasingly biases said transistor pair into heavy conduction only during high-to-low transitions. At all other times, the pull-down device is biased downwardly to deliver a low standby current to reduce dc power dissipation.